Vertical power devices, such as power field effect transistors and insulated gate bipolar transistors and power diodes, are sometimes manufactured on thinned wafers. In one exemplary manufacturing process, the front side of an ordinary monocrystalline silicon wafer of uniform thickness undergoes semiconductor fabrication processing such that the device sides of the power devices are formed into the front side of the wafer. One or more metallization layers are generally formed on the front side of the wafer to serve as front side electrodes of the power devices. In the case of a power field effect transistor or an insulated gate bipolar transistor, the control electrode is on the front side of the wafer. In the case of a power diode, the anode is on the front side of the wafer.
After this device formation has occurred, including all diffusion processing steps involved in the formation of the devices, the wafer is flipped over and a central portion of the back side of the wafer is thinned in what is often referred to as the Taiko grinding process. The outer peripheral rim portion of the back side of the wafer is, however, not thinned. As a result, a thicker peripheral edge support portion of the wafer is left surrounding a thinner central portion of the wafer. The thicker peripheral edge support portion provides mechanical stiffening such that the thinner central portion can be handled without cracking of the wafer. The thicker peripheral edge support portion also reduces wafer warpage in later processing steps.
After back side grinding, a back side metallization layer is formed on the thinner central portion of the back side of the wafer. This metallization forms electrodes on the back sides of the power devices. The peripheral edge support portion of the wafer is then cut off, and the thinner central portion of the wafer is diced to form individual power device dice.
In such a vertical power device die, on-state power loss generally occurs in the bulk of the device when current flows vertically from one side of the die, through the bulk of the device, and to the other side of the die. Reducing the resistance through the bulk of the die reduces on-state power loss. Accordingly, it is normally the goal of the device design engineer to reduce wafer thickness as much as possible as long as the required breakdown voltage of the power device is maintained. Vertical power devices are made in commercial processes on five inch wafers with suitable yields where the thin central portions of the Taiko wafers are as thin as about 200 microns.